The present patent application is related to co-pending patent application, entitled, xe2x80x9cSEMICONDUCTOR WAFER ANALYSIS SYSTEM AND METHOD,xe2x80x9d by Ehrichs and Wooten, now U.S. Pat. No. 6,156,580 issued Dec. 15, 2000, filed concurrent herewith, and assigned to the assignee of the present invention, the contents of which is hereby incorporated by reference.
The present invention is directed generally to semiconductor defect analysis, and more particularly to systems and method for review of semiconductor wafers.
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines.
In-line inspection and review are important for determining whether wafers have become contaminated with particles due to a tool malfunction or process problem. Contamination can lead to reduced yield. The xe2x80x9cinspectionxe2x80x9d of a wafer generally includes scanning the wafer with a laser and recording positions at which defects or particles deflect the laser. The positions are then used for xe2x80x9creviewxe2x80x9d of the wafer with a microscope. Inspection and review often take place at separate stations. Because contamination can cause stepper hot spots or further contamination of process tools, it is desirable to detect contamination before it creates further problems.
Therefore, it is desirable to provide a system and method that is better able to detect contamination and defects, as well as provide for improved review of wafers.
In various embodiments, the invention provides methods and systems for review of semiconductor wafers. In one embodiment, a method is provided that comprises downloading front side inspection data for the wafer from a control computer to a review station and positioning the wafer in response to the front side inspection data. The front side of the wafer is reviewed. The wafer is inverted, and back side inspection data for the wafer is downloaded from the control computer to the review station. The wafer is positioned in response to the back side inspection data, and the back side of the wafer is reviewed.
In another embodiment, a wafer review method comprises downloading front side inspection data for the wafer from a control computer to a first review station and positioning the wafer at the first review station in response to the front side inspection data. The wafer is reviewed and then moved to a second review station. The wafer is inverted, and back side inspection data for the wafer is downloaded from the control computer to the second review station. The wafer is then positioned at the second review station in response to the back side inspection data and thereafter reviewed.
In another embodiment, a semiconductor wafer review system is provided. The system comprises a robotic arm arranged to retrieve a wafer from a cassette. A wafer inverter is arranged to receive a wafer from the robotic arm, and a wafer transfer mechanism is arranged to receive the wafer from the wafer inverter and move the wafer. A microscope review station is arranged to receive the wafer from the wafer transfer mechanism and position the wafer for review with an objective.
A semiconductor wafer analysis system is provided in another embodiment. The system comprises a manufacturing control system arranged to transmit inspection data. A first review station is coupled to the control system and equipped with a microscope. The first review station is further arranged to receive wafer inspection data from the control system. A second review station is coupled to the control system and equipped with a microscope, and further arranged to receive inspection data from the control system. A wafer inverter is configured with the second review station and arranged to flip a wafer to be reviewed with the microscope of the second review station, whereby the backside of the wafer is exposed for viewing.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.